1 idt74fst3253 dual 4-bit to 1-bit fet multiplexer/demultiplexer industrial temperature range february 2000 1999 integrated device technology, inc. dsc-3968/- c idt74fst3253 industrial temperature range dual 4-bit to 1-bit fet multiplexer/ demultiplexer description: the fst3253 belongs to idt's family of bus switches. bus switch devices perform the function of connecting or isolating two ports without providing any inherent current sink or source capability. thus they generate little or no noise of their own while providing a low resistance path for an external driver. these devices connect input and output ports through an n-channel fet. when the gate-to-source junction of this fet is adequately forward-biased the device conducts or the resistance between input and output ports is small. without adequate bias on the gate-to-source junction of the fet, the fet is turned off, therefore with no v cc applied, the device has hot insertion capability. the low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero. the fst3253 is a dual, bidirectional 4 to 1 mux/demux. it is ideal for use in high speed interleaving or bus selection applications. 1 a 2 a 1 b 1 1 b 2 1 b 3 1 b 4 2 b 1 2 b 2 2 b 3 2 b 4 s 0 s 1 oe 2 oe 1 functional block diagram features: - bus switches provide zero delay paths - low switch on-resistance: 5 w - ttl-compatible input and output levels - esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) - available in qsop and soic packages
2 industrial temperature range idt74fst3253 dual 4-bit to 1-bit fet multiplexer/demultiplexer 5 6 7 8 1 2 3 4 14 13 12 11 10 9 1 b 1 1 b 2 1 a gnd vcc so16-1 so16-7 15 16 oe 1 1 b 3 1 b 4 s 1 oe 2 s 0 2 b 1 2 b 2 2 b 3 2 b 4 2 a soic/ qsop top view pin configuration capacitance (1) symbol parameter conditions (2) typ. unit c in control input capacitance 4 pf c i/o switch input/output capacitance switch off pf notes: 1. capacitance is characterized but not tested. 2. t a = 25c, f = 1mhz, v in = 0v, v out = 0v pin description pin names i/o description xa i/o muxed bus xby i/o demux bus oe x i output enable s 0 , s 1 i mux select functional table (1) s 1 s 0 oe 1 oe 2 function x x h x disconnect 1 a x x x h disconnect 2 a lll l 1 a to 1 b 1 and 2 a to 2 b 1 lhl l 1 a to 1 b 2 and 2 a to 2 b 2 hll l 1 a to 1 b 3 and 2 a to 2 b 3 hhl l 1 a to 1 b 4 and 2 a to 2 b 4 note: 1. h = high l = low x = dont care absolute maximum ratings (1) symbol rating max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7 v t stg storage temperature C65 to +150 c i out maximum continuous channel current 128 ma fst link notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. vcc, control, and switch terminals.
3 idt74fst3253 dual 4-bit to 1-bit fet multiplexer/demultiplexer industrial temperature range notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. measured by voltage drop between ports at indicated current through the switch. dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating conditions: t a = -40c to +85c, v cc = 5.0v 10% symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high voltage guaranteed logic high for control inputs 2 v v il input low voltage guaranteed logic low for control inputs 0.8 v i ih input high current v cc = max. v i = v cc 1a i il input low voltage v i = gnd 1 i ozh high impedance output current v cc = max. v o = v cc 1a i ozl (3-state output pins) v o = gnd 1 i os short circuit current v cc = max., v o = gnd (3) 300 ma v ik clamp diode voltage v cc = min., i in = C18ma C 0.7 C 1.2 v r on switch on resistance (4) v cc = min., v in = 0v, i on = 64ma 5 7 w v cc = min., v in = 0v, i on = 30ma 5 7 w v cc = min., v in = 2.4v, i on = 15ma 10 15 w i off input/output power off leakage v cc = 0v, v in or v o 4.5v 1a i cc quiescent power supply current v cc = max., v i = gnd or v cc 0.1 3 a
4 industrial temperature range idt74fst3253 dual 4-bit to 1-bit fet multiplexer/demultiplexer notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable dev ice type. 2. typical values are at v cc = 5.0v, +25c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f i n) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f i = input frequency n = number of switches toggling at f i all currents are in milliamps and all frequencies are in megahertz. notes: 1. see test circuit and waveforms. 2. minimum limits guaranteed but not tested. 3. this parameter is guaranteed by design but not tested. 4. the bus switch contributes no propagation delay other than the rc delay of the on resistance of the switch and the load capac itance. the time constant for the switch alone is of the order of 0.25 ns for 50 pf load. since this time is constant and much smaller than the rise/fal l times of typical driving signals, it adds very little propagation delay to the system. propagation delay of the bus switch when used in a system is determined b y the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5. measured at switch turn off, load = 50 pf in parallel with 10 m w scope probe, v in = 0.0 volts. 6. measured at switch turn off through bus multiplexer, (e.g.- b 1 to a = > b 2 to a), load = 50 pf in parallel with 10 m w scope probe, v in at a = 0.0 volts. charge injection is reduced because the injection from the turn off of the b 1 to a switch is compensated by the turn on of the b 2 to a switch. 7. characterized parameter. not 100% tested. power supply characteristics symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.51.5ma i ccd dynamic power supply current (4) v cc = max. outputs open v in = v cc v in = gnd a/ mhz/ one enable pin toggling 50% duty cycle switch i c total power supply current (6) v cc = max. outputs open two enable pins toggling v in = v cc v in = gnd ma (2 switches toggling) fi = 10mhz 50% duty cycle v in = 3.4 v in = gnd switching characteristics over operating range following conditions apply unless otherwise specified: operating conditions: t a = -40c to +85c, v cc = 5.0v 10% symbol description condition (1) min. (2) typ. max. unit t plh t phl data propagation delay xa to xby (3,4) c l = 50pf r l = 500 w 0.25 ns t bx switch multiplex delay sx to ax, xby 1.5 6.5 ns t pzh t pzl switch turn on delay oe to ax, xby 1.5 6.5 ns t phz t plz switch turn off delay oe to ax, xby (3) 1.5 5.5 ns |q ci | charge injection, typical (5,7) 1.5pc |q cdi | charge injection, typical (6,7) 0.5
5 idt74fst3253 dual 4-bit to 1-bit fet multiplexer/demultiplexer industrial temperature range pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. octal link octal link octal link octal link octal link test cir cuits and w a veforms propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times pulse width notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns switch position test switch open drain disable low closed enable low all other tests open fct link definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator.
6 industrial temperature range idt74fst3253 dual 4-bit to 1-bit fet multiplexer/demultiplexer corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information idt xx temp. range xx device type x package 74 - 40 c to +85 c so q 3253 small outline ic (so16-1) quarter-size small outline package (so16-7) dual 4 to 1 multiplexer/demultiplexer fst
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